An Effective Implementation of Dual Path Fused FloatingPoint AddSubtract Unit for Reconfigurable Architectures
Author(s):
Anitha Arumalla1*, Madhavi Latha Makkena2
Affiliations:
1Velagapudi Ramakrishna Siddhartha Engineering College, Vijayawada, India
2Jawaharlal Nehru Technological University Hyderabad, Hyderabad, India
Abstract:
Reconfigurable architectures have provided a low cost, fast turnaround platform for the development and deployment of designs in communication and signal processing applications. The floating point operations are used in most of the signal processing applications that require high precision and good accuracy. In this paper, an effective implementation of Fused Floatingpoint AddSubtract (FFAS) unit with a modification in dual path design is presented. To enhance the performance of FFAS unit for reconfigurable architectures, a dual path unit with a modification in close path design is proposed. The proposed design is targeted on a Xilinx Virtex6 device and implemented on ML605 Evaluation board for single, double and double extended precision. When compared to discrete floating point adder design, the FFAS unit reduces area requirement and power dissipation as the later shares common logic. A Dual Path FFAS (DPFFAS) unit has reduced latency when compared with FFAS unit. The latency is further reduced with the proposed modified DPFFAS when compared with DPFFAS for reconfigurable architectures.
Keywords:
Discrete floatingpoint design, Dual path algorithm, Floatingpoint arithmetic, Fused floatingpoint operation, Leading zero anticipation.
Full Text:
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